                                             
IBIS Macromodel Task Group

Meeting date: 13 Sep 2011

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                            * Radek Biernacki
Altera:                     * David Banas
Ansys:                        Samuel Mertens
                            * Dan Dvorscak
                            * Curtis Clark
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                        * Greg Edlund
Intel:                        Michael Mirmak
LSI Logic:                    Wenyi Jin
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
			      Vladimir Dmitriev-Zdorov
Micron Technology:            Randy Wolff
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:     * Eckhard Lenski
QLogic Corp.                * James Zhou
Sigrity:                      Brad Brim
                            * Kumar Keshavan
                              Ken Willis
SiSoft:                       Walter Katz
                            * Todd Westerhoff
                              Doug Burns
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla
unaffiliated:		   * Mike LaBonte

The meeting was lead by Arpad Muranyi

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Opens:

- Arpad: May have to leave soon, will leave meeting line open
  - Greg will discuss jitter parameters

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Call for patent disclosure:

- None

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Review of ARs:

- Arpad submit BIRD 137.2 to Open Forum
  - Done

- Arpad submit BIRD 143.1 to Open Forum
  - Done

- Mike post latest BIRD 123.2.3 to ATM web
  - Done just now 123.2.5

- Arpad: Inform Open Forum that BIRDs 137.1 and 143 will not change
  - Done, will be discussed Friday

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New Discussion:

Arpad showed BIRD 140.1:
- Arpad: Changes are near the bottom with **
  - A_to_D and D_to_A have another column
  - Has Format Corner specs
  - Examples added
  - New analysis added
- Radek: The official names of the corners are typ, min and max?
- Arpad: We might have to add mappings
- Radek: Min and max are OK, but we would want to avoid using slow and fast
- Arpad: We are really saying non-verbally what the mapping is
- Todd: In IBIS min means two things:
  - For most params slow/weak
  - For C_comp just the min value
  - Tools like SPICE have more then 3 combinations
  - I prefer slow/typ/fast
- Arpad: We can't change typ/min/max as the selector names
- Todd: It would be better to say min always means slow/weak except for C_comp
- Arpad: This BIRD is not written to solve that problem
- Ambrish: That one line should say typ/slow/fast
- Radek: If the model maker wants to use min and max values they will not use Corner
- Arpad: In the first section we don't explain what Corner does
- Todd: I drop my objection
  - Arpad is saying slow and fast are coming out of nowhere
  - IBIS says what min and max mean
  - Arpad just wants to extend that top AMI
  - We will go beyond 3 corners
  - The IBIS analog model can't go beyond 3 corners
- Arpad: Nothing keeps us from adding more columns
- Radek: Tying them together may be wrong for the future
- Ambrish: We would only have to add one line
- James: We should be able to do that
  - The real issue is what min/max means
- Ambrish: We only have to point to section 9 paragraph 2
- James: It should be clear what the model maker did to create each column
- Arpad: Is this BIRD acceptable as is?
- We will continue this topic next week

Todd showed Greg's jitter parameter document:
- Greg: These are all external to the DLL?
- Todd: Agree
- Kumar: Disagree
  - Assuming this is about BIRD 123
- Todd: This is about 5.0
- Kumar: RX Sj has to be handled by the CDR
  - Also RX_Receiver_Sensitivity
- Todd: What does the simulator do if it's in the AMI
- Kumar: It depends on the model
- David: Does external mean the DLL gives the EDA tool options?
  - Or does the tool tell the model how much it should be?
  - It would not make sense for the tool to make up values
- Arpad: Only the model maker knows
  - The tool should not have a say
- Todd showed the data format table
  - Range allows any value within constraints
- David: It comes from the model maker to say what the silicon does
- Todd: Yes
  - External means the DLL knows nothing about it
  - The simulator is expected to do something
  - Vih and Vil are handled that way
- David: "The model knows nothing about it" is confusing
  - It implies the model maker did not provide it
- Kumar: These are often like eye mask parameters
- Todd: The RX is guiding the post-processing of data
  - But the simulator handles it
- Arpad: Usually the outcome is an eye
  - How does RX_Receiver_Sensitivity fit in?
- David: It gives what you need to define eye width
- Arpad: Is this a poor man's way to define eye mask?
  - Usually Vinh and Vinl are used
- Todd: Anything between RX_RS would treated as impinging on an eye mask
- Fangyi: RX sens is used to calculate BER
  - That is not device behavior
  - The model should represent only device behavior
  - The EDA tool has to use this
- Todd: The RX models delivers clock_times and waveform at the sample latch
  - RX_RS tells us how to read the value there
  - No part of IBIS specifies an eye mask
- Fangyi: The eye is not sufficient
  - You have to know the model
- Todd: Yes several things are need to create an eye
- Todd slightly modified the first slide

Meeting ended.

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Next meeting: 20 Sep 2011 12:00pm PT

Next agenda:
1) Task list item discussions

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IBIS Interconnect SPICE Wish List:

1) Simulator directives
